Project Settings |
---|
Project Name | top_syn | Implementation Name | synthesis |
Top Module | work.top | Retiming | 0 |
Resource Sharing | 1 | Fanout Guide | 24 |
Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
24 |
0 |
0 |
- |
00m:00s |
- |
2018/06/06 22:32:15 |
(premap) | Complete |
3 |
1 |
0 |
0m:00s |
0m:00s |
109MB |
2018/06/06 22:32:16 |
(fpga_mapper) | Complete |
8 |
1 |
0 |
0m:00s |
0m:00s |
110MB |
2018/06/06 22:32:17 |
Multi-srs Generator |
Complete | | | | | | | 2018/06/06 22:32:16 |
Area Summary |
|
Core Cells | 68 |
IO Cells | 39 |
Block RAMs
(v_ram) | 0 |
| |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
top|CLK | 100.0 MHz | 94.3 MHz | -0.608 |
Optimizations Summary |
Combined Clock Conversion | 1 / 0 |
| |
|