#Build: Synplify Pro L-2016.09M-2, Build 065R, Nov 16 2016 #install: C:\Microsemi\Libero_SoC_v11.8\SynplifyPro #OS: Windows 8 6.2 #Hostname: H81I # Wed Jun 06 22:32:15 2018 #Implementation: synthesis Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys VHDL Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @N:CD720 : std.vhd(146) | Setting time resolution to ps @N: : top.vhd(17) | Top entity is set to top. File C:\Actelprj\test80_cpu\hdl\Decorder.vhd changed - recompiling File C:\Actelprj\test80_cpu\hdl\MUX.vhd changed - recompiling File C:\Actelprj\test80_cpu\hdl\PC.vhd changed - recompiling File C:\Actelprj\test80_cpu\hdl\regA.vhd changed - recompiling File C:\Actelprj\test80_cpu\hdl\regB.vhd changed - recompiling File C:\Actelprj\test80_cpu\hdl\regC.vhd changed - recompiling File C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\proasic\proasic3.vhd changed - recompiling VHDL syntax check successful! File C:\Actelprj\test80_cpu\hdl\Decorder.vhd changed - recompiling File C:\Actelprj\test80_cpu\hdl\MUX.vhd changed - recompiling File C:\Actelprj\test80_cpu\hdl\PC.vhd changed - recompiling File C:\Actelprj\test80_cpu\hdl\regA.vhd changed - recompiling File C:\Actelprj\test80_cpu\hdl\regB.vhd changed - recompiling File C:\Actelprj\test80_cpu\hdl\regC.vhd changed - recompiling @N:CD231 : std1164.vhd(890) | Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000". @N:CD630 : top.vhd(17) | Synthesizing work.top.rtl. @N:CD630 : regC.vhd(24) | Synthesizing work.regc.rtl. @N:CD364 : regC.vhd(52) | Removing redundant assignment. @N:CD364 : regC.vhd(55) | Removing redundant assignment. Post processing for work.regc.rtl @N:CD630 : regB.vhd(24) | Synthesizing work.regb.rtl. @N:CD364 : regB.vhd(52) | Removing redundant assignment. @N:CD364 : regB.vhd(55) | Removing redundant assignment. Post processing for work.regb.rtl @N:CD630 : regA.vhd(24) | Synthesizing work.rega.rtl. @N:CD364 : regA.vhd(52) | Removing redundant assignment. @N:CD364 : regA.vhd(55) | Removing redundant assignment. Post processing for work.rega.rtl @N:CD630 : PC.vhd(24) | Synthesizing work.pc.rtl. @N:CD364 : PC.vhd(55) | Removing redundant assignment. Post processing for work.pc.rtl @N:CD630 : MUX.vhd(24) | Synthesizing work.mux.rtl. @N:CD604 : MUX.vhd(49) | OTHERS clause is not synthesized. Post processing for work.mux.rtl @N:CD630 : Decorder.vhd(24) | Synthesizing work.decorder.rtl. Post processing for work.decorder.rtl @N:CD630 : CFlg.vhd(24) | Synthesizing work.cflg.rtl. @N:CD364 : CFlg.vhd(49) | Removing redundant assignment. Post processing for work.cflg.rtl @N:CD630 : ALU.vhd(24) | Synthesizing work.alu.rtl. Post processing for work.alu.rtl Post processing for work.top.rtl At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Jun 06 22:32:15 2018 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Jun 06 22:32:15 2018 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Jun 06 22:32:15 2018 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode File C:\Actelprj\test80_cpu\synthesis\synwork\top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Jun 06 22:32:16 2018 ###########################################################] Pre-mapping Report # Wed Jun 06 22:32:16 2018 Synopsys Microsemi Technology Pre-mapping, Version mapact, Build 1920R, Built Nov 17 2016 09:40:34 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) @A:MF827 : | No constraint file specified. Linked File: top_scck.rpt Printing clock summary report in "C:\Actelprj\test80_cpu\synthesis\top_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB) Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB) Clock Summary ***************** Start Requested Requested Clock Clock Clock Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------- top|CLK 100.0 MHz 10.000 inferred Inferred_clkgroup_0 20 ================================================================================== @W:MT530 : cflg.vhd(42) | Found inferred clock top|CLK which controls 20 sequential elements including CFlg_0.tmp. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\Actelprj\test80_cpu\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB) None None Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 109MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Jun 06 22:32:17 2018 ###########################################################] Map & Optimize Report # Wed Jun 06 22:32:17 2018 Synopsys Microsemi Technology Mapper, Version mapact, Build 1920R, Built Nov 17 2016 09:40:34 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB) @N:MF176 : | Default generator successful @N:MO106 : decorder.vhd(38) | Found ROM .delname. (in view: work.Decorder(rtl)) with 12 words by 2 bits. @N:MO231 : pc.vhd(42) | Found counter in view:work.PC(rtl) instance tmp[6:0] Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 110MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) @N:FP130 : | Promoting Net CLK_c on CLKBUF CLK_pad Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 20 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId0001 CLK port 20 regC_0.tmp[3] ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Writing Analyst data base C:\Actelprj\test80_cpu\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Writing EDIF Netlist and constraint files L-2016.09M-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Start final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) @W:MT420 : | Found inferred clock top|CLK with period 10.00ns. Please declare a user-defined clock on object "p:CLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Wed Jun 06 22:32:17 2018 # Top view: top Library name: PA3 Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: proasic3 Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -0.608 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------- top|CLK 100.0 MHz 94.3 MHz 10.000 10.608 -0.608 inferred Inferred_clkgroup_0 ====================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------- top|CLK top|CLK | 10.000 -0.608 | No paths - | No paths - | No paths - ========================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: top|CLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------- regB_0.tmp[0] top|CLK DFN1E1C0 Q QB_c[0] 0.737 -0.608 regA_0.tmp[0] top|CLK DFN1E1C0 Q QA_c[0] 0.580 -0.598 regB_0.tmp[1] top|CLK DFN1E1C0 Q QB_c[1] 0.737 0.728 regA_0.tmp[1] top|CLK DFN1E1C0 Q QA_c[1] 0.737 0.770 regB_0.tmp[2] top|CLK DFN1E1C0 Q QB_c[2] 0.737 1.611 regA_0.tmp[2] top|CLK DFN1E1C0 Q QA_c[2] 0.737 1.653 PC_0.tmp[0] top|CLK DFN1C0 Q Addr_c[0] 0.737 2.492 CFlg_0.tmp top|CLK DFN1C0 Q CFlg_0_Q 0.737 2.506 PC_0.tmp[1] top|CLK DFN1C0 Q Addr_c[1] 0.737 2.982 regB_0.tmp[3] top|CLK DFN1E1C0 Q QB_c[3] 0.737 3.061 ===================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------- PC_0.tmp[3] top|CLK DFN1C0 D tmp_n3 9.461 -0.608 PC_0.tmp[2] top|CLK DFN1C0 D tmp_n2 9.461 0.422 regC_0.tmp[3] top|CLK DFN1E1C0 D N_10_i 9.496 1.137 regB_0.tmp[3] top|CLK DFN1E1C0 D N_10_i 9.496 1.137 regA_0.tmp[3] top|CLK DFN1E1C0 D N_10_i 9.496 1.137 PC_0.tmp[1] top|CLK DFN1C0 D tmp_n1 9.461 1.540 regC_0.tmp[2] top|CLK DFN1E1C0 D N_12_i 9.496 2.167 regB_0.tmp[2] top|CLK DFN1E1C0 D N_12_i 9.496 2.167 regA_0.tmp[2] top|CLK DFN1E1C0 D N_12_i 9.496 2.167 PC_0.tmp[6] top|CLK DFN1C0 D tmp_n6 9.461 2.492 =================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 10.069 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.608 Number of logic level(s): 8 Starting point: regB_0.tmp[0] / Q Ending point: PC_0.tmp[3] / D The start point is clocked by top|CLK [rising] on pin CLK The end point is clocked by top|CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------ regB_0.tmp[0] DFN1E1C0 Q Out 0.737 0.737 - QB_c[0] Net - - 0.386 - 2 MUX_0.Y_2[0] NOR2A A In - 1.123 - MUX_0.Y_2[0] NOR2A Y Out 0.627 1.750 - N_20 Net - - 0.322 - 1 MUX_0.Y_3[0] MX2 B In - 2.072 - MUX_0.Y_3[0] MX2 Y Out 0.572 2.643 - MUX_0_Y[0] Net - - 0.386 - 2 ALU_0.un3_tmp.m1 NOR2B B In - 3.029 - ALU_0.un3_tmp.m1 NOR2B Y Out 0.627 3.657 - N_2_i Net - - 0.386 - 2 ALU_0.un3_tmp.m4 MIN3 B In - 4.042 - ALU_0.un3_tmp.m4 MIN3 Y Out 0.732 4.774 - i2_mux Net - - 0.386 - 2 ALU_0.un3_tmp.m7 AO18 B In - 5.160 - ALU_0.un3_tmp.m7 AO18 Y Out 0.645 5.805 - i4_mux Net - - 0.386 - 2 ALU_0.un3_tmp.m9 XNOR3 C In - 6.190 - ALU_0.un3_tmp.m9 XNOR3 Y Out 0.985 7.176 - N_10_i Net - - 1.184 - 4 PC_0.tmp_RNO_0[3] MX2 A In - 8.359 - PC_0.tmp_RNO_0[3] MX2 Y Out 0.579 8.938 - N_9 Net - - 0.322 - 1 PC_0.tmp_RNO[3] AX1C C In - 9.259 - PC_0.tmp_RNO[3] AX1C Y Out 0.488 9.748 - tmp_n3 Net - - 0.322 - 1 PC_0.tmp[3] DFN1C0 D In - 10.069 - ==================================================================================== Total path delay (propagation time + setup) of 10.608 is 6.531(61.6%) logic and 4.077(38.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 10.059 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.598 Number of logic level(s): 8 Starting point: regA_0.tmp[0] / Q Ending point: PC_0.tmp[3] / D The start point is clocked by top|CLK [rising] on pin CLK The end point is clocked by top|CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------ regA_0.tmp[0] DFN1E1C0 Q Out 0.580 0.580 - QA_c[0] Net - - 0.386 - 2 MUX_0.Y_1[0] MX2 A In - 0.966 - MUX_0.Y_1[0] MX2 Y Out 0.568 1.535 - N_28 Net - - 0.322 - 1 MUX_0.Y_3[0] MX2 A In - 1.856 - MUX_0.Y_3[0] MX2 Y Out 0.568 2.424 - MUX_0_Y[0] Net - - 0.386 - 2 ALU_0.un3_tmp.m1 NOR2B B In - 2.810 - ALU_0.un3_tmp.m1 NOR2B Y Out 0.516 3.326 - N_2_i Net - - 0.386 - 2 ALU_0.un3_tmp.m4 MIN3 B In - 3.712 - ALU_0.un3_tmp.m4 MIN3 Y Out 0.984 4.696 - i2_mux Net - - 0.386 - 2 ALU_0.un3_tmp.m7 AO18 B In - 5.082 - ALU_0.un3_tmp.m7 AO18 Y Out 0.713 5.794 - i4_mux Net - - 0.386 - 2 ALU_0.un3_tmp.m9 XNOR3 C In - 6.180 - ALU_0.un3_tmp.m9 XNOR3 Y Out 0.985 7.165 - N_10_i Net - - 1.184 - 4 PC_0.tmp_RNO_0[3] MX2 A In - 8.349 - PC_0.tmp_RNO_0[3] MX2 Y Out 0.579 8.928 - N_9 Net - - 0.322 - 1 PC_0.tmp_RNO[3] AX1C C In - 9.249 - PC_0.tmp_RNO[3] AX1C Y Out 0.488 9.737 - tmp_n3 Net - - 0.322 - 1 PC_0.tmp[3] DFN1C0 D In - 10.059 - ==================================================================================== Total path delay (propagation time + setup) of 10.598 is 6.520(61.5%) logic and 4.077(38.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 9.039 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.422 Number of logic level(s): 7 Starting point: regB_0.tmp[0] / Q Ending point: PC_0.tmp[2] / D The start point is clocked by top|CLK [rising] on pin CLK The end point is clocked by top|CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------ regB_0.tmp[0] DFN1E1C0 Q Out 0.737 0.737 - QB_c[0] Net - - 0.386 - 2 MUX_0.Y_2[0] NOR2A A In - 1.123 - MUX_0.Y_2[0] NOR2A Y Out 0.627 1.750 - N_20 Net - - 0.322 - 1 MUX_0.Y_3[0] MX2 B In - 2.072 - MUX_0.Y_3[0] MX2 Y Out 0.572 2.643 - MUX_0_Y[0] Net - - 0.386 - 2 ALU_0.un3_tmp.m1 NOR2B B In - 3.029 - ALU_0.un3_tmp.m1 NOR2B Y Out 0.627 3.657 - N_2_i Net - - 0.386 - 2 ALU_0.un3_tmp.m4 MIN3 B In - 4.042 - ALU_0.un3_tmp.m4 MIN3 Y Out 0.732 4.774 - i2_mux Net - - 0.386 - 2 ALU_0.un3_tmp.m11 XNOR3 C In - 5.160 - ALU_0.un3_tmp.m11 XNOR3 Y Out 0.985 6.145 - N_12_i Net - - 1.184 - 4 PC_0.tmp_RNO_0[2] MX2 A In - 7.329 - PC_0.tmp_RNO_0[2] MX2 Y Out 0.579 7.907 - N_7 Net - - 0.322 - 1 PC_0.tmp_RNO[2] AX1C C In - 8.229 - PC_0.tmp_RNO[2] AX1C Y Out 0.488 8.717 - tmp_n2 Net - - 0.322 - 1 PC_0.tmp[2] DFN1C0 D In - 9.039 - ==================================================================================== Total path delay (propagation time + setup) of 9.578 is 5.886(61.5%) logic and 3.691(38.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 8.960 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.501 Number of logic level(s): 7 Starting point: regA_0.tmp[0] / Q Ending point: PC_0.tmp[2] / D The start point is clocked by top|CLK [rising] on pin CLK The end point is clocked by top|CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------ regA_0.tmp[0] DFN1E1C0 Q Out 0.580 0.580 - QA_c[0] Net - - 0.386 - 2 MUX_0.Y_1[0] MX2 A In - 0.966 - MUX_0.Y_1[0] MX2 Y Out 0.568 1.535 - N_28 Net - - 0.322 - 1 MUX_0.Y_3[0] MX2 A In - 1.856 - MUX_0.Y_3[0] MX2 Y Out 0.568 2.424 - MUX_0_Y[0] Net - - 0.386 - 2 ALU_0.un3_tmp.m1 NOR2B B In - 2.810 - ALU_0.un3_tmp.m1 NOR2B Y Out 0.516 3.326 - N_2_i Net - - 0.386 - 2 ALU_0.un3_tmp.m4 MIN3 B In - 3.712 - ALU_0.un3_tmp.m4 MIN3 Y Out 0.984 4.696 - i2_mux Net - - 0.386 - 2 ALU_0.un3_tmp.m11 XNOR3 C In - 5.082 - ALU_0.un3_tmp.m11 XNOR3 Y Out 0.985 6.067 - N_12_i Net - - 1.184 - 4 PC_0.tmp_RNO_0[2] MX2 A In - 7.250 - PC_0.tmp_RNO_0[2] MX2 Y Out 0.579 7.829 - N_7 Net - - 0.322 - 1 PC_0.tmp_RNO[2] AX1C C In - 8.151 - PC_0.tmp_RNO[2] AX1C Y Out 0.488 8.639 - tmp_n2 Net - - 0.322 - 1 PC_0.tmp[2] DFN1C0 D In - 8.960 - ==================================================================================== Total path delay (propagation time + setup) of 9.499 is 5.808(61.1%) logic and 3.691(38.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 8.733 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.728 Number of logic level(s): 7 Starting point: regB_0.tmp[1] / Q Ending point: PC_0.tmp[3] / D The start point is clocked by top|CLK [rising] on pin CLK The end point is clocked by top|CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------ regB_0.tmp[1] DFN1E1C0 Q Out 0.737 0.737 - QB_c[1] Net - - 0.386 - 2 MUX_0.Y_2[1] NOR2A A In - 1.123 - MUX_0.Y_2[1] NOR2A Y Out 0.627 1.750 - N_21 Net - - 0.322 - 1 MUX_0.Y_3[1] MX2 B In - 2.072 - MUX_0.Y_3[1] MX2 Y Out 0.572 2.643 - MUX_0_Y[1] Net - - 0.386 - 2 ALU_0.un3_tmp.m4 MIN3 A In - 3.029 - ALU_0.un3_tmp.m4 MIN3 Y Out 0.408 3.438 - i2_mux Net - - 0.386 - 2 ALU_0.un3_tmp.m7 AO18 B In - 3.823 - ALU_0.un3_tmp.m7 AO18 Y Out 0.645 4.468 - i4_mux Net - - 0.386 - 2 ALU_0.un3_tmp.m9 XNOR3 C In - 4.854 - ALU_0.un3_tmp.m9 XNOR3 Y Out 0.985 5.839 - N_10_i Net - - 1.184 - 4 PC_0.tmp_RNO_0[3] MX2 A In - 7.023 - PC_0.tmp_RNO_0[3] MX2 Y Out 0.579 7.602 - N_9 Net - - 0.322 - 1 PC_0.tmp_RNO[3] AX1C C In - 7.923 - PC_0.tmp_RNO[3] AX1C Y Out 0.488 8.411 - tmp_n3 Net - - 0.322 - 1 PC_0.tmp[3] DFN1C0 D In - 8.733 - ==================================================================================== Total path delay (propagation time + setup) of 9.272 is 5.580(60.2%) logic and 3.691(39.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Finished timing report (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) -------------------------------------------------------------------------------- Target Part: A3PN250_VQFP100_STD Report for cell top.rtl Core Cell usage: cell count area count*area AO13 1 1.0 1.0 AO18 1 1.0 1.0 AOI1B 2 1.0 2.0 AX1C 4 1.0 4.0 GND 9 0.0 0.0 INV 3 1.0 3.0 MIN3 1 1.0 1.0 MX2 12 1.0 12.0 MX2A 1 1.0 1.0 MX2B 2 1.0 2.0 MX2C 1 1.0 1.0 NOR2A 5 1.0 5.0 NOR2B 5 1.0 5.0 NOR3C 2 1.0 2.0 OA1A 1 1.0 1.0 OR2A 1 1.0 1.0 VCC 9 0.0 0.0 XA1 2 1.0 2.0 XNOR3 2 1.0 2.0 XOR2 1 1.0 1.0 XOR3 1 1.0 1.0 DFN1C0 8 1.0 8.0 DFN1E1C0 12 1.0 12.0 ----- ---------- TOTAL 86 68.0 IO Cell usage: cell count CLKBUF 1 INBUF 13 OUTBUF 25 ----- TOTAL 39 Core Cells : 68 of 6144 (1%) IO Cells : 39 RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 24MB peak: 110MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Jun 06 22:32:17 2018 ###########################################################]