library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity PC_INCREMENTER is port( PCIINDATA : in std_logic_vector(8 downto 0); PCIOUTDATA : out std_logic_vector(8 downto 0)); end PC_INCREMENTER; architecture RTL of PC_INCREMENTER is begin PCIOUTDATA <= PCIINDATA + 1; end RTL;