-- VHDL Test Bench Created from source file statemachine8.vhd -- 04:55:39 01/22/2007 -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY statemachine8_statemachine8_driver_vhd_tb IS END statemachine8_statemachine8_driver_vhd_tb; ARCHITECTURE behavior OF statemachine8_statemachine8_driver_vhd_tb IS COMPONENT statemachine8 PORT( CLKIN : IN std_logic; DATAOUT : OUT std_logic_vector(7 downto 0) ); END COMPONENT; SIGNAL CLKIN : std_logic; SIGNAL DATAOUT : std_logic_vector(7 downto 0); BEGIN uut: statemachine8 PORT MAP( CLKIN => CLKIN, DATAOUT => DATAOUT ); -- *** Test Bench - User Defined Section *** tb : PROCESS BEGIN CLKIN <= '0'; wait for 1 ns; CLKIN <= '1'; wait for 1 ns; -- will wait forever END PROCESS; -- *** End Test Bench - User Defined Section *** END;