library IEEE; library UNISIM; use IEEE.std_logic_1164.all; use UNISIM.Vcomponents.all; use work.UPAC.all; entity STATEMACHINE9 is port ( CLKIN : in std_logic; DATAOUT : out std_logic_vector(7 downto 0) := "01010101" ); end STATEMACHINE9; architecture RTL of STATEMACHINE9 is component BUNSHUU port ( CLKIN : in std_logic; CLKOUT : out std_logic); end component; component STATE_GENERATOR port ( CLK : in std_logic; RESET : in std_logic; STATEIN : in STATE; STATEOUT : out STATE); end component; component CONTROLLER port ( STATEIN : in STATE; CODEIN : in std_logic_vector(5 downto 0); STATEOUT : out STATE; CODEOUT : out std_logic_vector(5 downto 0); I, J, B, PCWEN : out std_logic; --immediate,jump,branch signal MUX : out std_logic_vector(1 downto 0); --multiplexer ENA, ENB, SSRA, SSRB, WEA, WEB : out std_logic; EN, SSR, WE : out std_logic; LED : out std_logic); end component; component ALU3 port ( A,B : in std_logic_vector(31 downto 0); CODE : in std_logic_vector(5 downto 0); DOUT : out std_logic_vector(31 downto 0); Z : out std_logic); end component; component PC port ( PCINDATA : in std_logic_vector(8 downto 0); PCOUTDATA : out std_logic_vector(8 downto 0); PCCLK : in std_logic; PCWRITE_EN : in std_logic; PCRESET : in std_logic); end component; component PC_INCREMENTER port ( PCIINDATA : in std_logic_vector(8 downto 0); PCIOUTDATA : out std_logic_vector(8 downto 0)); end component; component ANDGATE port ( A, B : in std_logic; C : out std_logic ); end component; component SELECTOR port ( A, B : in std_logic_vector(8 downto 0); SEL : in std_logic; OUTDATA : out std_logic_vector(8 downto 0)); end component; component SELECTOR2 port ( A, B : in std_logic_vector(31 downto 0); SEL : in std_logic; OUTDATA : out std_logic_vector(31 downto 0)); end component; component SELECTOR3 port ( A,B,C : in std_logic_vector(4 downto 0); SEL : in std_logic_vector(1 downto 0); DATA : out std_logic_vector(8 downto 0)); end component; signal SIGCLK,SIGCLK2,SIGCLEAR,SIGPCWE,SIGI,SIGB,SIGJ,ZFLAG,SEL2IN : std_logic; signal ALUOP,SIGCODE : std_logic_vector(5 downto 0); signal SIGPCIN,SIGPCOUT,SIGPCIOUT,SEL2OUT,BTARGET,JTARGET : std_logic_vector(8 downto 0); signal ALUINB,ALUOUT,SEL3INA,IMMEDIATE : std_logic_vector(31 downto 0); signal AD1A,AD1B : std_logic_vector(8 downto 0); signal EN1A,EN1B,EN2,RES1A,RES1B,RES2,WE1A,WE1B,WE2,SIGLED : std_logic; signal DI2,DO2,DI1A,DI1B,DO1A : std_logic_vector(31 downto 0); signal DIP1A,DIP1B,DIP2 : std_logic_vector(3 downto 0); signal CURRENTSTATE,NEXTSTATE : STATE; signal SIGMUX : std_logic_vector(1 downto 0); begin AD1B <= "0000"&DO2(20 downto 16); SIGCODE <= DO2(31 downto 26); IMMEDIATE <= "0000000000000000"&DO2(15 downto 0); JTARGET <= DO2(8 downto 0); BTARGET <= DO2(8 downto 0); DI1A <= ALUOUT; process(SIGLED) begin if SIGLED'event and SIGLED='1' then DATAOUT <= not DO1A(7 downto 0); else null; end if; end process; BUNSHUU0 : BUNSHUU port map ( CLKIN => SIGCLK2, CLKOUT => SIGCLK); ALU0 : ALU3 port map ( A => DO1A, B => ALUINB, CODE => ALUOP, DOUT => ALUOUT, Z => ZFLAG); PC0 : PC port map ( PCCLK => SIGCLK, PCRESET => SIGCLEAR, PCWRITE_EN => SIGPCWE, PCINDATA => SIGPCIN, PCOUTDATA => SIGPCOUT); PCI0 : PC_INCREMENTER port map ( PCIINDATA => SIGPCOUT, PCIOUTDATA => SIGPCIOUT); AND0 : ANDGATE port map ( A => ZFLAG, B => SIGB, C => SEL2IN); SEL1 : SELECTOR port map ( A => SEL2OUT, B => JTARGET, SEL => SIGJ, OUTDATA => SIGPCIN); SEL2 : SELECTOR port map ( A => SIGPCIOUT, B => BTARGET, SEL => SEL2IN, OUTDATA => SEL2OUT); SEL3 : SELECTOR2 port map ( A => SEL3INA, B => IMMEDIATE, SEL => SIGI, OUTDATA => ALUINB); MUX3 : SELECTOR3 port map ( A => DO2(25 downto 21), B => DO2(20 downto 16), C => DO2(15 downto 11), SEL => SIGMUX, DATA => AD1A); CONTROLLER0 : CONTROLLER port map ( STATEIN => CURRENTSTATE, CODEIN => SIGCODE, STATEOUT => NEXTSTATE, CODEOUT => ALUOP, I => SIGI, B => SIGB, J => SIGJ, PCWEN => SIGPCWE, MUX => SIGMUX, ENA => EN1A, ENB => EN1B, SSRA => RES1A, SSRB => RES1B, WEA => WE1A, WEB => WE1B, EN => EN2, SSR => RES2, WE => WE2, LED => SIGLED); STATE_GENERATOR0 : STATE_GENERATOR port map ( CLK => SIGCLK, RESET => SIGCLEAR, STATEIN => NEXTSTATE, STATEOUT => CURRENTSTATE); IBG : IBUFG port map ( I => CLKIN, O => SIGCLK2); RC : ROC port map ( O => SIGCLEAR); INSTMEM : RAMB16_S36 generic map ( write_mode => "WRITE_FIRST", -- initialize instruction memory -- addr 000000000 : LOOP1 : beq r1,r2,RET1 -- addr 000000001 : add r4,r3,r4 -- addr 000000010 : addi r2,r2,1 -- addr 000000011 : led r4 -- addr 000000100 : jump LOOP2 -- addr 000000101 : LOOP2 : beq r1,r2,RET2 -- addr 000000110 : add r3,r3,r4 -- addr 000000111 : addi r2,r2,1 -- addr 000001000 : led r3 -- addr 000001001 : jump LOOP1 -- addr 000001010 : RET1 : addi r5,r3,0 -- addr 000001011 : : stop -- addr 000001100 : RET2 : addi r5,r4,0 -- addr 000001101 : : stop INIT_00 => X"08420001046418000C22000C100000051480000008420001046420000C22000A", INIT_01 => X"0000000000000000180000000885000018000000086500001000000014600000") port map ( ADDR => SIGPCOUT, CLK => SIGCLK, EN => EN2, SSR => RES2, WE => WE2, DI => DI2, DIP => DIP2, DO => DO2); REGFILE : RAMB16_S36_S36 generic map ( WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", -- initialize register file -- addr 000000000 : r0=0(constant zero register) -- addr 000000001 : r1=13 -- addr 000000010 : r2=1(for-loop counter) -- addr 000000011 : r3=1(fib(1)) -- addr 000000100 : r4=0(fib(0)) INIT_00 => X"0000000000000000000000000000000000000001000000010000000D00000000") port map ( ADDRA => AD1A, ADDRB => AD1B, CLKA => SIGCLK, CLKB => SIGCLK, ENA => EN1A, ENB => EN1B, SSRA => RES1A, SSRB => RES1B, WEA => WE1A, WEB => WE1B, DIA => DI1A, DIB => DI1B, DIPA => DIP1A, DIPB => DIP1B, DOA => DO1A, DOB => SEL3INA); end RTL;