library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; entity BUNSHUU is port ( CLKIN : in std_logic; CLKOUT : out std_logic := '0'); end BUNSHUU; architecture RTL of BUNSHUU is signal counter : std_logic_vector(26 downto 0):= "000000000000000000000000000"; begin process (CLKIN) begin if(CLKIN'event and CLKIN='1') then counter <= counter + 1; if(counter="000001111111111111111111111") then CLKOUT <= '1'; elsif(counter="000011111111111111111111111") then counter <= "000000000000000000000000000"; CLKOUT <= '0'; end if; end if; end process; end RTL;