モジュール | |
LPC11xx CMSIS Definitions | |
LPC11xx System Control Block | |
LPC11xx I/O Configuration Block | |
LPC11xx Power Management Unit | |
LPC11xx General Purpose Input/Output | |
LPC11xx 16/32-bit Counter/Timer | |
LPC11xx Universal Asynchronous Receiver/Transmitter | |
LPC11xx Synchronous Serial Port | |
LPC11xx I2C-Bus Interface | |
LPC11xx WatchDog Timer | |
LPC11xx Analog-to-Digital Converter | |
LPC11xx Controller Area Network(CAN) | |
マクロ定義 | |
#define | LPC_FLASH_BASE (0x00000000UL) |
#define | LPC_RAM_BASE (0x10000000UL) |
#define | LPC_APB0_BASE (0x40000000UL) |
#define | LPC_AHB_BASE (0x50000000UL) |
#define | LPC_I2C_BASE (LPC_APB0_BASE + 0x00000) |
#define | LPC_WDT_BASE (LPC_APB0_BASE + 0x04000) |
#define | LPC_UART_BASE (LPC_APB0_BASE + 0x08000) |
#define | LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000) |
#define | LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000) |
#define | LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000) |
#define | LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000) |
#define | LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000) |
#define | LPC_PMU_BASE (LPC_APB0_BASE + 0x38000) |
#define | LPC_SSP0_BASE (LPC_APB0_BASE + 0x40000) |
#define | LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) |
#define | LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) |
#define | LPC_CAN_BASE (LPC_APB0_BASE + 0x50000) |
#define | LPC_SSP1_BASE (LPC_APB0_BASE + 0x58000) |
#define | LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000) |
#define | LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000) |
#define | LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000) |
#define | LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000) |
#define | LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000) |
#define | LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) |
#define | LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) |
#define | LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE ) |
#define | LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE) |
#define | LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE) |
#define | LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE) |
#define | LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE) |
#define | LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) |
#define | LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) |
#define | LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) |
#define | LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) |
#define | LPC_CAN ((LPC_CAN_TypeDef *) LPC_CAN_BASE ) |
#define | LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) |
#define | LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) |
#define | LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) |
#define | LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) |
#define | LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) |
#define | LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) |
変数 | |
__IO uint32_t | LPC_SYSCON_TypeDef::PRESETCTRL |
__IO uint32_t | LPC_SYSCON_TypeDef::SYSPLLCTRL |
__IO uint32_t | LPC_SYSCON_TypeDef::SYSPLLSTAT |
uint32_t | LPC_SYSCON_TypeDef::RESERVED0 [4] |
__IO uint32_t | LPC_SYSCON_TypeDef::SYSOSCCTRL |
__IO uint32_t | LPC_SYSCON_TypeDef::WDTOSCCTRL |
__IO uint32_t | LPC_SYSCON_TypeDef::IRCCTRL |
uint32_t | LPC_SYSCON_TypeDef::RESERVED1 [1] |
__IO uint32_t | LPC_SYSCON_TypeDef::SYSRESSTAT |
uint32_t | LPC_SYSCON_TypeDef::RESERVED2 [3] |
__IO uint32_t | LPC_SYSCON_TypeDef::SYSPLLCLKSEL |
__IO uint32_t | LPC_SYSCON_TypeDef::SYSPLLCLKUEN |
uint32_t | LPC_SYSCON_TypeDef::RESERVED3 [10] |
__IO uint32_t | LPC_SYSCON_TypeDef::MAINCLKSEL |
__IO uint32_t | LPC_SYSCON_TypeDef::MAINCLKUEN |
__IO uint32_t | LPC_SYSCON_TypeDef::SYSAHBCLKDIV |
uint32_t | LPC_SYSCON_TypeDef::RESERVED4 [1] |
__IO uint32_t | LPC_SYSCON_TypeDef::SYSAHBCLKCTRL |
uint32_t | LPC_SYSCON_TypeDef::RESERVED5 [4] |
__IO uint32_t | LPC_SYSCON_TypeDef::SSP0CLKDIV |
__IO uint32_t | LPC_SYSCON_TypeDef::UARTCLKDIV |
__IO uint32_t | LPC_SYSCON_TypeDef::SSP1CLKDIV |
uint32_t | LPC_SYSCON_TypeDef::RESERVED6 [4] |
__IO uint32_t | LPC_SYSCON_TypeDef::SYSTICKCLKDIV |
uint32_t | LPC_SYSCON_TypeDef::RESERVED7 [7] |
__IO uint32_t | LPC_SYSCON_TypeDef::WDTCLKSEL |
__IO uint32_t | LPC_SYSCON_TypeDef::WDTCLKUEN |
__IO uint32_t | LPC_SYSCON_TypeDef::WDTCLKDIV |
uint32_t | LPC_SYSCON_TypeDef::RESERVED8 [1] |
__IO uint32_t | LPC_SYSCON_TypeDef::CLKOUTCLKSEL |
__IO uint32_t | LPC_SYSCON_TypeDef::CLKOUTUEN |
__IO uint32_t | LPC_SYSCON_TypeDef::CLKOUTDIV |
uint32_t | LPC_SYSCON_TypeDef::RESERVED9 [5] |
__IO uint32_t | LPC_SYSCON_TypeDef::PIOPORCAP0 |
__IO uint32_t | LPC_SYSCON_TypeDef::PIOPORCAP1 |
uint32_t | LPC_SYSCON_TypeDef::RESERVED10 [18] |
__IO uint32_t | LPC_SYSCON_TypeDef::BODCTRL |
uint32_t | LPC_SYSCON_TypeDef::RESERVED11 [1] |
__IO uint32_t | LPC_SYSCON_TypeDef::SYSTCKCAL |
uint32_t | LPC_SYSCON_TypeDef::RESERVED12 |
__IO uint32_t | LPC_SYSCON_TypeDef::MAINREGVOUT0CFG |
__IO uint32_t | LPC_SYSCON_TypeDef::MAINREGVOUT1CFG |
uint32_t | LPC_SYSCON_TypeDef::RESERVED13 [38] |
__IO uint32_t | LPC_SYSCON_TypeDef::STARTAPRP0 |
__IO uint32_t | LPC_SYSCON_TypeDef::STARTERP0 |
__IO uint32_t | LPC_SYSCON_TypeDef::STARTRSRP0CLR |
__IO uint32_t | LPC_SYSCON_TypeDef::STARTSRP0 |
uint32_t | LPC_SYSCON_TypeDef::RESERVED14 [8] |
__IO uint32_t | LPC_SYSCON_TypeDef::PDSLEEPCFG |
__IO uint32_t | LPC_SYSCON_TypeDef::PDAWAKECFG |
__IO uint32_t | LPC_SYSCON_TypeDef::PDRUNCFG |
uint32_t | LPC_SYSCON_TypeDef::RESERVED15 [101] |
__O uint32_t | LPC_SYSCON_TypeDef::VOUTCFGPROT |
uint32_t | LPC_SYSCON_TypeDef::RESERVED16 [8] |
__I uint32_t | LPC_SYSCON_TypeDef::DEVICE_ID |
uint32_t | LPC_IOCON_TypeDef::RESERVED0 [1] |
__IO uint32_t | LPC_IOCON_TypeDef::PIO2_0 |
__IO uint32_t | LPC_IOCON_TypeDef::RESET_PIO0_0 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO0_1 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO1_8 |
uint32_t | LPC_IOCON_TypeDef::RESERVED1 [1] |
__IO uint32_t | LPC_IOCON_TypeDef::PIO0_2 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO2_7 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO2_8 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO2_1 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO0_3 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO0_4 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO0_5 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO1_9 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO3_4 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO2_4 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO2_5 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO3_5 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO0_6 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO0_7 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO2_9 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO2_10 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO2_2 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO0_8 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO0_9 |
__IO uint32_t | LPC_IOCON_TypeDef::SWCLK_PIO0_10 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO1_10 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO2_11 |
__IO uint32_t | LPC_IOCON_TypeDef::R_PIO0_11 |
__IO uint32_t | LPC_IOCON_TypeDef::R_PIO1_0 |
__IO uint32_t | LPC_IOCON_TypeDef::R_PIO1_1 |
__IO uint32_t | LPC_IOCON_TypeDef::R_PIO1_2 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO3_0 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO3_1 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO2_3 |
__IO uint32_t | LPC_IOCON_TypeDef::SWDIO_PIO1_3 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO1_4 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO1_11 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO3_2 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO1_5 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO1_6 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO1_7 |
__IO uint32_t | LPC_IOCON_TypeDef::PIO3_3 |
__IO uint32_t | LPC_IOCON_TypeDef::SCK_LOC |
__IO uint32_t | LPC_IOCON_TypeDef::DSR_LOC |
__IO uint32_t | LPC_IOCON_TypeDef::DCD_LOC |
__IO uint32_t | LPC_IOCON_TypeDef::RI_LOC |
__IO uint32_t | LPC_PMU_TypeDef::GPREG0 |
__IO uint32_t | LPC_PMU_TypeDef::GPREG1 |
__IO uint32_t | LPC_PMU_TypeDef::GPREG2 |
__IO uint32_t | LPC_PMU_TypeDef::GPREG3 |
__IO uint32_t | LPC_PMU_TypeDef::GPREG4 |
__IO uint32_t LPC_GPIO_TypeDef::DATA | |
struct { | |
uint32_t RESERVED0 [4095] | |
__IO uint32_t LPC_GPIO_TypeDef::DATA | |
} | |
uint32_t | LPC_GPIO_TypeDef::RESERVED1 [4096] |
__IO uint32_t | LPC_GPIO_TypeDef::DIR |
__IO uint32_t | LPC_GPIO_TypeDef::IS |
__IO uint32_t | LPC_GPIO_TypeDef::IBE |
__IO uint32_t | LPC_GPIO_TypeDef::IEV |
__IO uint32_t | LPC_GPIO_TypeDef::IE |
__IO uint32_t | LPC_GPIO_TypeDef::RIS |
__IO uint32_t | LPC_GPIO_TypeDef::MIS |
__IO uint32_t | LPC_GPIO_TypeDef::IC |
__IO uint32_t | LPC_TMR_TypeDef::TCR |
__IO uint32_t | LPC_TMR_TypeDef::TC |
__IO uint32_t | LPC_TMR_TypeDef::PR |
__IO uint32_t | LPC_TMR_TypeDef::PC |
__IO uint32_t | LPC_TMR_TypeDef::MCR |
__IO uint32_t | LPC_TMR_TypeDef::MR0 |
__IO uint32_t | LPC_TMR_TypeDef::MR1 |
__IO uint32_t | LPC_TMR_TypeDef::MR2 |
__IO uint32_t | LPC_TMR_TypeDef::MR3 |
__IO uint32_t | LPC_TMR_TypeDef::CCR |
__I uint32_t | LPC_TMR_TypeDef::CR0 |
uint32_t | LPC_TMR_TypeDef::RESERVED1 [3] |
__IO uint32_t | LPC_TMR_TypeDef::EMR |
uint32_t | LPC_TMR_TypeDef::RESERVED2 [12] |
__IO uint32_t | LPC_TMR_TypeDef::CTCR |
__IO uint32_t | LPC_TMR_TypeDef::PWMC |
__O uint32_t LPC_UART_TypeDef::THR | |
__IO uint32_t LPC_UART_TypeDef::DLL | |
__IO uint32_t LPC_UART_TypeDef::IER | |
union { | |
__IO uint32_t DLM | |
__IO uint32_t LPC_UART_TypeDef::IER | |
}; | |
__O uint32_t LPC_UART_TypeDef::FCR | |
union { | |
__I uint32_t IIR | |
__O uint32_t LPC_UART_TypeDef::FCR | |
}; | |
__IO uint32_t | LPC_UART_TypeDef::LCR |
__IO uint32_t | LPC_UART_TypeDef::MCR |
__I uint32_t | LPC_UART_TypeDef::LSR |
__I uint32_t | LPC_UART_TypeDef::MSR |
__IO uint32_t | LPC_UART_TypeDef::SCR |
__IO uint32_t | LPC_UART_TypeDef::ACR |
uint32_t | LPC_UART_TypeDef::RESERVED0 |
__IO uint32_t | LPC_UART_TypeDef::FDR |
uint32_t | LPC_UART_TypeDef::RESERVED1 |
__IO uint32_t | LPC_UART_TypeDef::TER |
uint32_t | LPC_UART_TypeDef::RESERVED2 [6] |
__IO uint32_t | LPC_UART_TypeDef::RS485CTRL |
__IO uint32_t | LPC_UART_TypeDef::ADRMATCH |
__IO uint32_t | LPC_UART_TypeDef::RS485DLY |
__I uint32_t | LPC_UART_TypeDef::FIFOLVL |
__IO uint32_t | LPC_SSP_TypeDef::CR1 |
__IO uint32_t | LPC_SSP_TypeDef::DR |
__I uint32_t | LPC_SSP_TypeDef::SR |
__IO uint32_t | LPC_SSP_TypeDef::CPSR |
__IO uint32_t | LPC_SSP_TypeDef::IMSC |
__IO uint32_t | LPC_SSP_TypeDef::RIS |
__IO uint32_t | LPC_SSP_TypeDef::MIS |
__IO uint32_t | LPC_SSP_TypeDef::ICR |
__I uint32_t | LPC_I2C_TypeDef::STAT |
__IO uint32_t | LPC_I2C_TypeDef::DAT |
__IO uint32_t | LPC_I2C_TypeDef::ADR0 |
__IO uint32_t | LPC_I2C_TypeDef::SCLH |
__IO uint32_t | LPC_I2C_TypeDef::SCLL |
__O uint32_t | LPC_I2C_TypeDef::CONCLR |
__IO uint32_t | LPC_I2C_TypeDef::MMCTRL |
__IO uint32_t | LPC_I2C_TypeDef::ADR1 |
__IO uint32_t | LPC_I2C_TypeDef::ADR2 |
__IO uint32_t | LPC_I2C_TypeDef::ADR3 |
__I uint32_t | LPC_I2C_TypeDef::DATA_BUFFER |
__IO uint32_t | LPC_I2C_TypeDef::MASK0 |
__IO uint32_t | LPC_I2C_TypeDef::MASK1 |
__IO uint32_t | LPC_I2C_TypeDef::MASK2 |
__IO uint32_t | LPC_I2C_TypeDef::MASK3 |
__IO uint32_t | LPC_WDT_TypeDef::TC |
__O uint32_t | LPC_WDT_TypeDef::FEED |
__I uint32_t | LPC_WDT_TypeDef::TV |
uint32_t | LPC_WDT_TypeDef::RESERVED0 |
__IO uint32_t | LPC_WDT_TypeDef::WARNINT |
__IO uint32_t | LPC_WDT_TypeDef::WINDOW |
__IO uint32_t | LPC_ADC_TypeDef::GDR |
uint32_t | LPC_ADC_TypeDef::RESERVED0 |
__IO uint32_t | LPC_ADC_TypeDef::INTEN |
__IO uint32_t | LPC_ADC_TypeDef::DR [8] |
__I uint32_t | LPC_ADC_TypeDef::STAT |
__IO uint32_t | LPC_CAN_TypeDef::STAT |
__IO uint32_t | LPC_CAN_TypeDef::EC |
__IO uint32_t | LPC_CAN_TypeDef::BT |
__IO uint32_t | LPC_CAN_TypeDef::INT |
__IO uint32_t | LPC_CAN_TypeDef::TEST |
__IO uint32_t | LPC_CAN_TypeDef::BRPE |
uint32_t | LPC_CAN_TypeDef::RESERVED0 |
__IO uint32_t | LPC_CAN_TypeDef::IF1_CMDREQ |
__IO uint32_t | LPC_CAN_TypeDef::IF1_CMDMSK |
__IO uint32_t | LPC_CAN_TypeDef::IF1_MSK1 |
__IO uint32_t | LPC_CAN_TypeDef::IF1_MSK2 |
__IO uint32_t | LPC_CAN_TypeDef::IF1_ARB1 |
__IO uint32_t | LPC_CAN_TypeDef::IF1_ARB2 |
__IO uint32_t | LPC_CAN_TypeDef::IF1_MCTRL |
__IO uint32_t | LPC_CAN_TypeDef::IF1_DA1 |
__IO uint32_t | LPC_CAN_TypeDef::IF1_DA2 |
__IO uint32_t | LPC_CAN_TypeDef::IF1_DB1 |
__IO uint32_t | LPC_CAN_TypeDef::IF1_DB2 |
uint32_t | LPC_CAN_TypeDef::RESERVED1 [13] |
__IO uint32_t | LPC_CAN_TypeDef::IF2_CMDREQ |
__IO uint32_t | LPC_CAN_TypeDef::IF2_CMDMSK |
__IO uint32_t | LPC_CAN_TypeDef::IF2_MSK1 |
__IO uint32_t | LPC_CAN_TypeDef::IF2_MSK2 |
__IO uint32_t | LPC_CAN_TypeDef::IF2_ARB1 |
__IO uint32_t | LPC_CAN_TypeDef::IF2_ARB2 |
__IO uint32_t | LPC_CAN_TypeDef::IF2_MCTRL |
__IO uint32_t | LPC_CAN_TypeDef::IF2_DA1 |
__IO uint32_t | LPC_CAN_TypeDef::IF2_DA2 |
__IO uint32_t | LPC_CAN_TypeDef::IF2_DB1 |
__IO uint32_t | LPC_CAN_TypeDef::IF2_DB2 |
uint32_t | LPC_CAN_TypeDef::RESERVED2 [21] |
__I uint32_t | LPC_CAN_TypeDef::TXREQ1 |
__I uint32_t | LPC_CAN_TypeDef::TXREQ2 |
uint32_t | LPC_CAN_TypeDef::RESERVED3 [6] |
__I uint32_t | LPC_CAN_TypeDef::ND1 |
__I uint32_t | LPC_CAN_TypeDef::ND2 |
uint32_t | LPC_CAN_TypeDef::RESERVED4 [6] |
__I uint32_t | LPC_CAN_TypeDef::IR1 |
__I uint32_t | LPC_CAN_TypeDef::IR2 |
uint32_t | LPC_CAN_TypeDef::RESERVED5 [6] |
__I uint32_t | LPC_CAN_TypeDef::MSGV1 |
__I uint32_t | LPC_CAN_TypeDef::MSGV2 |
uint32_t | LPC_CAN_TypeDef::RESERVED6 [6] |
__IO uint32_t | LPC_CAN_TypeDef::CLKDIV |
This file defines all structures and symbols for LPC11xx:
__IO uint32_t LPC_UART_TypeDef::ACR |
Offset: 0x020 Auto-baud Control Register (R/W)
__IO uint32_t LPC_I2C_TypeDef::ADR0 |
Offset: 0x00C I2C Slave Address Register 0 (R/W)
__IO uint32_t LPC_I2C_TypeDef::ADR1 |
Offset: 0x020 I2C Slave Address Register 1 (R/W)
__IO uint32_t LPC_I2C_TypeDef::ADR2 |
Offset: 0x024 I2C Slave Address Register 2 (R/W)
__IO uint32_t LPC_I2C_TypeDef::ADR3 |
Offset: 0x028 I2C Slave Address Register 3 (R/W)
__IO uint32_t LPC_UART_TypeDef::ADRMATCH |
Offset: 0x050 RS-485/EIA-485 address match Register (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::BODCTRL |
Offset: 0x150 BOD control (R/W)
__IO uint32_t LPC_TMR_TypeDef::CCR |
Offset: 0x028 Capture Control Register (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::CLKOUTCLKSEL |
Offset: 0x0E0 CLKOUT clock source select (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::CLKOUTDIV |
Offset: 0x0E8 CLKOUT clock divider (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::CLKOUTUEN |
Offset: 0x0E4 CLKOUT clock source update enable (R/W)
__O uint32_t LPC_I2C_TypeDef::CONCLR |
Offset: 0x018 I2C Control Clear Register ( /W)
__IO uint32_t LPC_SSP_TypeDef::CPSR |
Offset: 0x010 Clock Prescale Register (R/W)
__I uint32_t LPC_TMR_TypeDef::CR0 |
Offset: 0x02C Capture Register 0 (R/ )
__IO uint32_t LPC_SSP_TypeDef::CR1 |
Offset: 0x004 Control Register 1 (R/W)
__IO uint32_t LPC_TMR_TypeDef::CTCR |
Offset: 0x070 Count Control Register (R/W)
__IO uint32_t LPC_I2C_TypeDef::DAT |
Offset: 0x008 I2C Data Register (R/W)
__IO uint32_t LPC_GPIO_TypeDef::DATA |
Offset: 0x3FFC Port data Register (R/W)
__IO { ... } ::DATA |
Offset: 0x3FFC Port data Register (R/W)
__I uint32_t LPC_I2C_TypeDef::DATA_BUFFER |
Offset: 0x02C Data buffer register ( /W)
__IO uint32_t LPC_IOCON_TypeDef::DCD_LOC |
Offset: 0x0B8 DCD pin location select Register (R/W)
__I uint32_t LPC_SYSCON_TypeDef::DEVICE_ID |
Offset: 0x3F4 Device ID (R/ )
__IO uint32_t LPC_GPIO_TypeDef::DIR |
Offset: 0x8000 Data direction Register (R/W)
__IO uint32_t LPC_UART_TypeDef::DLL |
Offset: 0x000 Divisor Latch LSB (R/W)
__IO { ... } ::DLL |
Offset: 0x000 Divisor Latch LSB (R/W)
__IO { ... } ::DLM |
Offset: 0x004 Divisor Latch MSB (R/W)
__IO uint32_t LPC_SSP_TypeDef::DR |
Offset: 0x008 Data Register (R/W)
__IO uint32_t LPC_ADC_TypeDef::DR[8] |
Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W)
__IO uint32_t LPC_IOCON_TypeDef::DSR_LOC |
Offset: 0x0B4 DSR pin location select Register (R/W)
__IO uint32_t LPC_TMR_TypeDef::EMR |
Offset: 0x03C External Match Register (R/W)
__O uint32_t LPC_UART_TypeDef::FCR |
Offset: 0x008 FIFO Control Register ( /W)
__O { ... } ::FCR |
Offset: 0x008 FIFO Control Register ( /W)
__IO uint32_t LPC_UART_TypeDef::FDR |
Offset: 0x028 Fractional Divider Register (R/W)
__O uint32_t LPC_WDT_TypeDef::FEED |
Offset: 0x008 Watchdog feed sequence register ( /W)
__I uint32_t LPC_UART_TypeDef::FIFOLVL |
Offset: 0x058 FIFO Level Register (R/ )
__IO uint32_t LPC_ADC_TypeDef::GDR |
Offset: 0x004 A/D Global Data Register (R/W)
__IO uint32_t LPC_PMU_TypeDef::GPREG0 |
Offset: 0x004 General purpose Register 0 (R/W)
__IO uint32_t LPC_PMU_TypeDef::GPREG1 |
Offset: 0x008 General purpose Register 1 (R/W)
__IO uint32_t LPC_PMU_TypeDef::GPREG2 |
Offset: 0x00C General purpose Register 2 (R/W)
__IO uint32_t LPC_PMU_TypeDef::GPREG3 |
Offset: 0x010 General purpose Register 3 (R/W)
__IO uint32_t LPC_PMU_TypeDef::GPREG4 |
Offset: 0x014 General purpose Register 4 (R/W)
__IO uint32_t LPC_GPIO_TypeDef::IBE |
Offset: 0x8008 Interrupt both edges Register (R/W)
__IO uint32_t LPC_GPIO_TypeDef::IC |
Offset: 0x801C Interrupt clear Register (R/W)
__IO uint32_t LPC_SSP_TypeDef::ICR |
Offset: 0x020 SSPICR Interrupt Clear Register (R/W)
__IO uint32_t LPC_GPIO_TypeDef::IE |
Offset: 0x8010 Interrupt mask Register (R/W)
__IO uint32_t LPC_UART_TypeDef::IER |
Offset: 0x000 Interrupt Enable Register (R/W)
__IO { ... } ::IER |
Offset: 0x000 Interrupt Enable Register (R/W)
__IO uint32_t LPC_GPIO_TypeDef::IEV |
Offset: 0x800C Interrupt event Register (R/W)
__I { ... } ::IIR |
Offset: 0x008 Interrupt ID Register (R/ )
__IO uint32_t LPC_SSP_TypeDef::IMSC |
Offset: 0x014 Interrupt Mask Set and Clear Register (R/W)
__IO uint32_t LPC_ADC_TypeDef::INTEN |
Offset: 0x00C A/D Interrupt Enable Register (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::IRCCTRL |
Offset: 0x028 IRC control (R/W)
__IO uint32_t LPC_GPIO_TypeDef::IS |
Offset: 0x8004 Interrupt sense Register (R/W)
__IO uint32_t LPC_UART_TypeDef::LCR |
Offset: 0x00C Line Control Register (R/W)
__I uint32_t LPC_UART_TypeDef::LSR |
Offset: 0x014 Line Status Register (R/ )
__IO uint32_t LPC_SYSCON_TypeDef::MAINCLKSEL |
Offset: 0x070 Main clock source select (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::MAINCLKUEN |
Offset: 0x074 Main clock source update enable (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::MAINREGVOUT0CFG |
Offset: 0x160 Main Regulator Voltage 0 Configuration
__IO uint32_t LPC_SYSCON_TypeDef::MAINREGVOUT1CFG |
Offset: 0x164 Main Regulator Voltage 1 Configuration
__IO uint32_t LPC_I2C_TypeDef::MASK0 |
Offset: 0x030 I2C Slave address mask register 0 (R/W)
__IO uint32_t LPC_I2C_TypeDef::MASK1 |
Offset: 0x034 I2C Slave address mask register 1 (R/W)
__IO uint32_t LPC_I2C_TypeDef::MASK2 |
Offset: 0x038 I2C Slave address mask register 2 (R/W)
__IO uint32_t LPC_I2C_TypeDef::MASK3 |
Offset: 0x03C I2C Slave address mask register 3 (R/W)
__IO uint32_t LPC_UART_TypeDef::MCR |
Offset: 0x010 Modem control Register (R/W)
__IO uint32_t LPC_TMR_TypeDef::MCR |
Offset: 0x014 Match Control Register (R/W)
__IO uint32_t LPC_SSP_TypeDef::MIS |
Offset: 0x01C Masked Interrupt Status Register (R/W)
__IO uint32_t LPC_GPIO_TypeDef::MIS |
Offset: 0x8018 Masked interrupt status Register (R/ )
__IO uint32_t LPC_I2C_TypeDef::MMCTRL |
Offset: 0x01C Monitor mode control register (R/W)
__IO uint32_t LPC_TMR_TypeDef::MR0 |
Offset: 0x018 Match Register 0 (R/W)
__IO uint32_t LPC_TMR_TypeDef::MR1 |
Offset: 0x01C Match Register 1 (R/W)
__IO uint32_t LPC_TMR_TypeDef::MR2 |
Offset: 0x020 Match Register 2 (R/W)
__IO uint32_t LPC_TMR_TypeDef::MR3 |
Offset: 0x024 Match Register 3 (R/W)
__I uint32_t LPC_UART_TypeDef::MSR |
Offset: 0x018 Modem status Register (R/ )
__IO uint32_t LPC_TMR_TypeDef::PC |
Offset: 0x010 Prescale Counter Register (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::PDAWAKECFG |
Offset: 0x234 Power-down states after wake-up (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::PDRUNCFG |
Offset: 0x238 Power-down configuration Register (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::PDSLEEPCFG |
Offset: 0x230 Power-down states in Deep-sleep mode (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO0_1 |
Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO0_2 |
Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO0_3 |
Offset: 0x02C I/O configuration for pin PIO0_3 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO0_4 |
Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO0_5 |
Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO0_6 |
Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO0_7 |
Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO0_8 |
Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO0_9 |
Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO1_10 |
Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO1_11 |
Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO1_4 |
Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO1_5 |
Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO1_6 |
Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO1_7 |
Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO1_8 |
Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO1_9 |
Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO2_0 |
Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO2_1 |
Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO2_10 |
Offset: 0x058 I/O configuration for pin PIO2_10 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO2_11 |
Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO2_2 |
Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO2_3 |
Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO2_4 |
Offset: 0x040 I/O configuration for pin PIO2_4 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO2_5 |
Offset: 0x044 I/O configuration for pin PIO2_5 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO2_7 |
Offset: 0x020 I/O configuration for pin PIO2_7 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO2_8 |
Offset: 0x024 I/O configuration for pin PIO2_8 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO2_9 |
Offset: 0x054 I/O configuration for pin PIO2_9 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO3_0 |
Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO3_1 |
Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO3_2 |
Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO3_3 |
Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO3_4 |
Offset: 0x03C I/O configuration for pin PIO3_4 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::PIO3_5 |
Offset: 0x048 I/O configuration for pin PIO3_5 (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::PIOPORCAP0 |
Offset: 0x100 POR captured PIO status 0 (R/ )
__IO uint32_t LPC_SYSCON_TypeDef::PIOPORCAP1 |
Offset: 0x104 POR captured PIO status 1 (R/ )
__IO uint32_t LPC_TMR_TypeDef::PR |
Offset: 0x00C Prescale Register (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::PRESETCTRL |
Offset: 0x004 Peripheral reset control (R/W)
__IO uint32_t LPC_TMR_TypeDef::PWMC |
Offset: 0x074 PWM Control Register (R/W)
__IO uint32_t LPC_IOCON_TypeDef::R_PIO0_11 |
Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::R_PIO1_0 |
Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::R_PIO1_1 |
Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::R_PIO1_2 |
Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::RESET_PIO0_0 |
Offset: 0x00C I/O configuration for pin RESET/PIO0_0 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::RI_LOC |
Offset: 0x0BC RI pin location Register (R/W)
__IO uint32_t LPC_SSP_TypeDef::RIS |
Offset: 0x018 Raw Interrupt Status Register (R/W)
__IO uint32_t LPC_GPIO_TypeDef::RIS |
Offset: 0x8014 Raw interrupt status Register (R/ )
__IO uint32_t LPC_UART_TypeDef::RS485CTRL |
Offset: 0x04C RS-485/EIA-485 Control Register (R/W)
__IO uint32_t LPC_UART_TypeDef::RS485DLY |
Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W)
__IO uint32_t LPC_IOCON_TypeDef::SCK_LOC |
Offset: 0x0B0 SCK pin location select Register (R/W)
__IO uint32_t LPC_I2C_TypeDef::SCLH |
Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W)
__IO uint32_t LPC_I2C_TypeDef::SCLL |
Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W)
__IO uint32_t LPC_UART_TypeDef::SCR |
Offset: 0x01C Scratch Pad Register (R/W)
__I uint32_t LPC_SSP_TypeDef::SR |
Offset: 0x00C Status Registe (R/ )
__IO uint32_t LPC_SYSCON_TypeDef::SSP0CLKDIV |
Offset: 0x094 SSP0 clock divider (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::SSP1CLKDIV |
Offset: 0x09C SSP1 clock divider (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::STARTAPRP0 |
Offset: 0x200 Start logic edge control Register 0 (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::STARTERP0 |
Offset: 0x204 Start logic signal enable Register 0 (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::STARTRSRP0CLR |
Offset: 0x208 Start logic reset Register 0 ( /W)
__IO uint32_t LPC_SYSCON_TypeDef::STARTSRP0 |
Offset: 0x20C Start logic status Register 0 (R/W)
__I uint32_t LPC_ADC_TypeDef::STAT |
Offset: 0x030 A/D Status Register (R/ )
__I uint32_t LPC_I2C_TypeDef::STAT |
Offset: 0x004 I2C Status Register (R/ )
__IO uint32_t LPC_IOCON_TypeDef::SWCLK_PIO0_10 |
Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W)
__IO uint32_t LPC_IOCON_TypeDef::SWDIO_PIO1_3 |
Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::SYSAHBCLKCTRL |
Offset: 0x080 System AHB clock control (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::SYSAHBCLKDIV |
Offset: 0x078 System AHB clock divider (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::SYSOSCCTRL |
Offset: 0x020 System oscillator control (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::SYSPLLCLKSEL |
Offset: 0x040 System PLL clock source select (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::SYSPLLCLKUEN |
Offset: 0x044 System PLL clock source update enable (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::SYSPLLCTRL |
Offset: 0x008 System PLL control (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::SYSPLLSTAT |
Offset: 0x00C System PLL status (R/ )
__IO uint32_t LPC_SYSCON_TypeDef::SYSRESSTAT |
Offset: 0x030 System reset status Register (R/ )
__IO uint32_t LPC_SYSCON_TypeDef::SYSTCKCAL |
Offset: 0x158 System tick counter calibration (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::SYSTICKCLKDIV |
Offset: 0x0B0 SYSTICK clock divider (R/W)
__IO uint32_t LPC_TMR_TypeDef::TC |
Offset: 0x008 Timer Counter Register (R/W)
__IO uint32_t LPC_WDT_TypeDef::TC |
Offset: 0x004 Watchdog timer constant register (R/W)
__IO uint32_t LPC_TMR_TypeDef::TCR |
Offset: 0x004 Timer Control Register (R/W)
__IO uint32_t LPC_UART_TypeDef::TER |
Offset: 0x030 Transmit Enable Register (R/W)
__O uint32_t LPC_UART_TypeDef::THR |
Offset: 0x000 Transmit Holding Register ( /W)
__O { ... } ::THR |
Offset: 0x000 Transmit Holding Register ( /W)
__I uint32_t LPC_WDT_TypeDef::TV |
Offset: 0x00C Watchdog timer value register (R/ )
__IO uint32_t LPC_SYSCON_TypeDef::UARTCLKDIV |
Offset: 0x098 UART clock divider (R/W)
__O uint32_t LPC_SYSCON_TypeDef::VOUTCFGPROT |
Offset: 0x3D0 Voltage Output Configuration Protection Register (W)
__IO uint32_t LPC_SYSCON_TypeDef::WDTCLKDIV |
Offset: 0x0D8 WDT clock divider (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::WDTCLKSEL |
Offset: 0x0D0 WDT clock source select (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::WDTCLKUEN |
Offset: 0x0D4 WDT clock source update enable (R/W)
__IO uint32_t LPC_SYSCON_TypeDef::WDTOSCCTRL |
Offset: 0x024 Watchdog oscillator control (R/W)