構成 | |
struct | SCB_Type |
マクロ定義 | |
#define | SCB_CPUID_IMPLEMENTER_Pos 24 |
#define | SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) |
#define | SCB_CPUID_VARIANT_Pos 20 |
#define | SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) |
#define | SCB_CPUID_ARCHITECTURE_Pos 16 |
#define | SCB_CPUID_ARCHITECTURE_Msk (0xFul << SCB_CPUID_ARCHITECTURE_Pos) |
#define | SCB_CPUID_PARTNO_Pos 4 |
#define | SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) |
#define | SCB_CPUID_REVISION_Pos 0 |
#define | SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) |
#define | SCB_ICSR_NMIPENDSET_Pos 31 |
#define | SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) |
#define | SCB_ICSR_PENDSVSET_Pos 28 |
#define | SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) |
#define | SCB_ICSR_PENDSVCLR_Pos 27 |
#define | SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) |
#define | SCB_ICSR_PENDSTSET_Pos 26 |
#define | SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) |
#define | SCB_ICSR_PENDSTCLR_Pos 25 |
#define | SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) |
#define | SCB_ICSR_ISRPREEMPT_Pos 23 |
#define | SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) |
#define | SCB_ICSR_ISRPENDING_Pos 22 |
#define | SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) |
#define | SCB_ICSR_VECTPENDING_Pos 12 |
#define | SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) |
#define | SCB_ICSR_VECTACTIVE_Pos 0 |
#define | SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) |
#define | SCB_AIRCR_VECTKEY_Pos 16 |
#define | SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) |
#define | SCB_AIRCR_VECTKEYSTAT_Pos 16 |
#define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) |
#define | SCB_AIRCR_ENDIANESS_Pos 15 |
#define | SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) |
#define | SCB_AIRCR_SYSRESETREQ_Pos 2 |
#define | SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) |
#define | SCB_AIRCR_VECTCLRACTIVE_Pos 1 |
#define | SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) |
#define | SCB_SCR_SEVONPEND_Pos 4 |
#define | SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) |
#define | SCB_SCR_SLEEPDEEP_Pos 2 |
#define | SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) |
#define | SCB_SCR_SLEEPONEXIT_Pos 1 |
#define | SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) |
#define | SCB_CCR_STKALIGN_Pos 9 |
#define | SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) |
#define | SCB_CCR_UNALIGN_TRP_Pos 3 |
#define | SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) |
#define | SCB_SHCSR_SVCALLPENDED_Pos 15 |
#define | SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) |
#define | SCB_DFSR_EXTERNAL_Pos 4 |
#define | SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) |
#define | SCB_DFSR_VCATCH_Pos 3 |
#define | SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) |
#define | SCB_DFSR_DWTTRAP_Pos 2 |
#define | SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) |
#define | SCB_DFSR_BKPT_Pos 1 |
#define | SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) |
#define | SCB_DFSR_HALTED_Pos 0 |
#define | SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) |
memory mapped structure for System Control Block (SCB)
#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
#define SCB_AIRCR_ENDIANESS_Pos 15 |
SCB AIRCR: ENDIANESS Position
#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
#define SCB_AIRCR_SYSRESETREQ_Pos 2 |
SCB AIRCR: SYSRESETREQ Position
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 |
SCB AIRCR: VECTCLRACTIVE Position
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
#define SCB_AIRCR_VECTKEY_Pos 16 |
SCB AIRCR: VECTKEY Position
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 |
SCB AIRCR: VECTKEYSTAT Position
#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
#define SCB_CCR_STKALIGN_Pos 9 |
SCB CCR: STKALIGN Position
#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
#define SCB_CCR_UNALIGN_TRP_Pos 3 |
SCB CCR: UNALIGN_TRP Position
#define SCB_CPUID_ARCHITECTURE_Msk (0xFul << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
#define SCB_CPUID_ARCHITECTURE_Pos 16 |
SCB CPUID: ARCHITECTURE Position
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
#define SCB_CPUID_IMPLEMENTER_Pos 24 |
SCB CPUID: IMPLEMENTER Position
#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
#define SCB_CPUID_PARTNO_Pos 4 |
SCB CPUID: PARTNO Position
#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) |
SCB CPUID: REVISION Mask
#define SCB_CPUID_REVISION_Pos 0 |
SCB CPUID: REVISION Position
#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
#define SCB_CPUID_VARIANT_Pos 20 |
SCB CPUID: VARIANT Position
#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
#define SCB_DFSR_BKPT_Pos 1 |
SCB DFSR: BKPT Position
#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
#define SCB_DFSR_DWTTRAP_Pos 2 |
SCB DFSR: DWTTRAP Position
#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
#define SCB_DFSR_EXTERNAL_Pos 4 |
SCB DFSR: EXTERNAL Position
#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) |
SCB DFSR: HALTED Mask
#define SCB_DFSR_HALTED_Pos 0 |
SCB DFSR: HALTED Position
#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
#define SCB_DFSR_VCATCH_Pos 3 |
SCB DFSR: VCATCH Position
#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
#define SCB_ICSR_ISRPENDING_Pos 22 |
SCB ICSR: ISRPENDING Position
#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
#define SCB_ICSR_ISRPREEMPT_Pos 23 |
SCB ICSR: ISRPREEMPT Position
#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
#define SCB_ICSR_NMIPENDSET_Pos 31 |
SCB ICSR: NMIPENDSET Position
#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
#define SCB_ICSR_PENDSTCLR_Pos 25 |
SCB ICSR: PENDSTCLR Position
#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
#define SCB_ICSR_PENDSTSET_Pos 26 |
SCB ICSR: PENDSTSET Position
#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
#define SCB_ICSR_PENDSVCLR_Pos 27 |
SCB ICSR: PENDSVCLR Position
#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
#define SCB_ICSR_PENDSVSET_Pos 28 |
SCB ICSR: PENDSVSET Position
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) |
SCB ICSR: VECTACTIVE Mask
#define SCB_ICSR_VECTACTIVE_Pos 0 |
SCB ICSR: VECTACTIVE Position
#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
#define SCB_ICSR_VECTPENDING_Pos 12 |
SCB ICSR: VECTPENDING Position
#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
#define SCB_SCR_SEVONPEND_Pos 4 |
SCB SCR: SEVONPEND Position
#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
#define SCB_SCR_SLEEPDEEP_Pos 2 |
SCB SCR: SLEEPDEEP Position
#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
#define SCB_SCR_SLEEPONEXIT_Pos 1 |
SCB SCR: SLEEPONEXIT Position
#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
#define SCB_SHCSR_SVCALLPENDED_Pos 15 |
SCB SHCSR: SVCALLPENDED Position