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00020
00021 #ifndef __LPC11xx_H__
00022 #define __LPC11xx_H__
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00038
00039
00040
00046
00047
00048
00049
00050
00051
00052 typedef enum IRQn
00053 {
00054
00055 NonMaskableInt_IRQn = -14,
00056 HardFault_IRQn = -13,
00057 SVCall_IRQn = -5,
00058 PendSV_IRQn = -2,
00059 SysTick_IRQn = -1,
00061
00062 WAKEUP0_IRQn = 0,
00063 WAKEUP1_IRQn = 1,
00064 WAKEUP2_IRQn = 2,
00065 WAKEUP3_IRQn = 3,
00066 WAKEUP4_IRQn = 4,
00067 WAKEUP5_IRQn = 5,
00068 WAKEUP6_IRQn = 6,
00069 WAKEUP7_IRQn = 7,
00070 WAKEUP8_IRQn = 8,
00071 WAKEUP9_IRQn = 9,
00072 WAKEUP10_IRQn = 10,
00073 WAKEUP11_IRQn = 11,
00074 WAKEUP12_IRQn = 12,
00075 CAN_IRQn = 13,
00076 SSP1_IRQn = 14,
00077 I2C_IRQn = 15,
00078 TIMER_16_0_IRQn = 16,
00079 TIMER_16_1_IRQn = 17,
00080 TIMER_32_0_IRQn = 18,
00081 TIMER_32_1_IRQn = 19,
00082 SSP0_IRQn = 20,
00083 UART_IRQn = 21,
00084 ADC_IRQn = 24,
00085 WDT_IRQn = 25,
00086 BOD_IRQn = 26,
00087 EINT3_IRQn = 28,
00088 EINT2_IRQn = 29,
00089 EINT1_IRQn = 30,
00090 EINT0_IRQn = 31,
00091 } IRQn_Type;
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101 #define __MPU_PRESENT 0
00102 #define __NVIC_PRIO_BITS 2
00103 #define __Vendor_SysTickConfig 0
00105
00106
00107
00108 #include "core_cm0.h"
00109 #include "system_LPC11xx.h"
00110
00111
00112
00113
00114
00115
00116 #if defined ( __CC_ARM )
00117 #pragma anon_unions
00118 #endif
00119
00120
00124 typedef struct
00125 {
00126 __IO uint32_t SYSMEMREMAP;
00127 __IO uint32_t PRESETCTRL;
00128 __IO uint32_t SYSPLLCTRL;
00129 __IO uint32_t SYSPLLSTAT;
00130 uint32_t RESERVED0[4];
00131
00132 __IO uint32_t SYSOSCCTRL;
00133 __IO uint32_t WDTOSCCTRL;
00134 __IO uint32_t IRCCTRL;
00135 uint32_t RESERVED1[1];
00136 __IO uint32_t SYSRESSTAT;
00137 uint32_t RESERVED2[3];
00138 __IO uint32_t SYSPLLCLKSEL;
00139 __IO uint32_t SYSPLLCLKUEN;
00140 uint32_t RESERVED3[10];
00141
00142 __IO uint32_t MAINCLKSEL;
00143 __IO uint32_t MAINCLKUEN;
00144 __IO uint32_t SYSAHBCLKDIV;
00145 uint32_t RESERVED4[1];
00146
00147 __IO uint32_t SYSAHBCLKCTRL;
00148 uint32_t RESERVED5[4];
00149 __IO uint32_t SSP0CLKDIV;
00150 __IO uint32_t UARTCLKDIV;
00151 __IO uint32_t SSP1CLKDIV;
00152 uint32_t RESERVED6[4];
00153
00154 __IO uint32_t SYSTICKCLKDIV;
00155 uint32_t RESERVED7[7];
00156
00157 __IO uint32_t WDTCLKSEL;
00158 __IO uint32_t WDTCLKUEN;
00159 __IO uint32_t WDTCLKDIV;
00160 uint32_t RESERVED8[1];
00161 __IO uint32_t CLKOUTCLKSEL;
00162 __IO uint32_t CLKOUTUEN;
00163 __IO uint32_t CLKOUTDIV;
00164 uint32_t RESERVED9[5];
00165
00166 __IO uint32_t PIOPORCAP0;
00167 __IO uint32_t PIOPORCAP1;
00168 uint32_t RESERVED10[18];
00169
00170 __IO uint32_t BODCTRL;
00171 uint32_t RESERVED11[1];
00172 __IO uint32_t SYSTCKCAL;
00173 uint32_t RESERVED12;
00174 __IO uint32_t MAINREGVOUT0CFG;
00175 __IO uint32_t MAINREGVOUT1CFG;
00176 uint32_t RESERVED13[38];
00177
00178 __IO uint32_t STARTAPRP0;
00179 __IO uint32_t STARTERP0;
00180 __IO uint32_t STARTRSRP0CLR;
00181 __IO uint32_t STARTSRP0;
00182 uint32_t RESERVED14[8];
00183
00184 __IO uint32_t PDSLEEPCFG;
00185 __IO uint32_t PDAWAKECFG;
00186 __IO uint32_t PDRUNCFG;
00187 uint32_t RESERVED15[101];
00188 __O uint32_t VOUTCFGPROT;
00189 uint32_t RESERVED16[8];
00190 __I uint32_t DEVICE_ID;
00191 } LPC_SYSCON_TypeDef;
00193
00194
00195
00199 typedef struct
00200 {
00201 __IO uint32_t PIO2_6;
00202 uint32_t RESERVED0[1];
00203 __IO uint32_t PIO2_0;
00204 __IO uint32_t RESET_PIO0_0;
00205 __IO uint32_t PIO0_1;
00206 __IO uint32_t PIO1_8;
00207 uint32_t RESERVED1[1];
00208 __IO uint32_t PIO0_2;
00210 __IO uint32_t PIO2_7;
00211 __IO uint32_t PIO2_8;
00212 __IO uint32_t PIO2_1;
00213 __IO uint32_t PIO0_3;
00214 __IO uint32_t PIO0_4;
00215 __IO uint32_t PIO0_5;
00216 __IO uint32_t PIO1_9;
00217 __IO uint32_t PIO3_4;
00219 __IO uint32_t PIO2_4;
00220 __IO uint32_t PIO2_5;
00221 __IO uint32_t PIO3_5;
00222 __IO uint32_t PIO0_6;
00223 __IO uint32_t PIO0_7;
00224 __IO uint32_t PIO2_9;
00225 __IO uint32_t PIO2_10;
00226 __IO uint32_t PIO2_2;
00228 __IO uint32_t PIO0_8;
00229 __IO uint32_t PIO0_9;
00230 __IO uint32_t SWCLK_PIO0_10;
00231 __IO uint32_t PIO1_10;
00232 __IO uint32_t PIO2_11;
00233 __IO uint32_t R_PIO0_11;
00234 __IO uint32_t R_PIO1_0;
00235 __IO uint32_t R_PIO1_1;
00237 __IO uint32_t R_PIO1_2;
00238 __IO uint32_t PIO3_0;
00239 __IO uint32_t PIO3_1;
00240 __IO uint32_t PIO2_3;
00241 __IO uint32_t SWDIO_PIO1_3;
00242 __IO uint32_t PIO1_4;
00243 __IO uint32_t PIO1_11;
00244 __IO uint32_t PIO3_2;
00246 __IO uint32_t PIO1_5;
00247 __IO uint32_t PIO1_6;
00248 __IO uint32_t PIO1_7;
00249 __IO uint32_t PIO3_3;
00250 __IO uint32_t SCK_LOC;
00251 __IO uint32_t DSR_LOC;
00252 __IO uint32_t DCD_LOC;
00253 __IO uint32_t RI_LOC;
00254 } LPC_IOCON_TypeDef;
00256
00257
00258
00262 typedef struct
00263 {
00264 __IO uint32_t PCON;
00265 __IO uint32_t GPREG0;
00266 __IO uint32_t GPREG1;
00267 __IO uint32_t GPREG2;
00268 __IO uint32_t GPREG3;
00269 __IO uint32_t GPREG4;
00270 } LPC_PMU_TypeDef;
00272
00273
00274
00278 typedef struct
00279 {
00280 union {
00281 __IO uint32_t MASKED_ACCESS[4096];
00282 struct {
00283 uint32_t RESERVED0[4095];
00284 __IO uint32_t DATA;
00285 };
00286 };
00287 uint32_t RESERVED1[4096];
00288 __IO uint32_t DIR;
00289 __IO uint32_t IS;
00290 __IO uint32_t IBE;
00291 __IO uint32_t IEV;
00292 __IO uint32_t IE;
00293 __IO uint32_t RIS;
00294 __IO uint32_t MIS;
00295 __IO uint32_t IC;
00296 } LPC_GPIO_TypeDef;
00298
00299
00300
00304 typedef struct
00305 {
00306 __IO uint32_t IR;
00307 __IO uint32_t TCR;
00308 __IO uint32_t TC;
00309 __IO uint32_t PR;
00310 __IO uint32_t PC;
00311 __IO uint32_t MCR;
00312 __IO uint32_t MR0;
00313 __IO uint32_t MR1;
00314 __IO uint32_t MR2;
00315 __IO uint32_t MR3;
00316 __IO uint32_t CCR;
00317 __I uint32_t CR0;
00318 uint32_t RESERVED1[3];
00319 __IO uint32_t EMR;
00320 uint32_t RESERVED2[12];
00321 __IO uint32_t CTCR;
00322 __IO uint32_t PWMC;
00323 } LPC_TMR_TypeDef;
00325
00326
00327
00331 typedef struct
00332 {
00333 union {
00334 __I uint32_t RBR;
00335 __O uint32_t THR;
00336 __IO uint32_t DLL;
00337 };
00338 union {
00339 __IO uint32_t DLM;
00340 __IO uint32_t IER;
00341 };
00342 union {
00343 __I uint32_t IIR;
00344 __O uint32_t FCR;
00345 };
00346 __IO uint32_t LCR;
00347 __IO uint32_t MCR;
00348 __I uint32_t LSR;
00349 __I uint32_t MSR;
00350 __IO uint32_t SCR;
00351 __IO uint32_t ACR;
00352 uint32_t RESERVED0;
00353 __IO uint32_t FDR;
00354 uint32_t RESERVED1;
00355 __IO uint32_t TER;
00356 uint32_t RESERVED2[6];
00357 __IO uint32_t RS485CTRL;
00358 __IO uint32_t ADRMATCH;
00359 __IO uint32_t RS485DLY;
00360 __I uint32_t FIFOLVL;
00361 } LPC_UART_TypeDef;
00363
00364
00365
00369 typedef struct
00370 {
00371 __IO uint32_t CR0;
00372 __IO uint32_t CR1;
00373 __IO uint32_t DR;
00374 __I uint32_t SR;
00375 __IO uint32_t CPSR;
00376 __IO uint32_t IMSC;
00377 __IO uint32_t RIS;
00378 __IO uint32_t MIS;
00379 __IO uint32_t ICR;
00380 } LPC_SSP_TypeDef;
00382
00383
00384
00388 typedef struct
00389 {
00390 __IO uint32_t CONSET;
00391 __I uint32_t STAT;
00392 __IO uint32_t DAT;
00393 __IO uint32_t ADR0;
00394 __IO uint32_t SCLH;
00395 __IO uint32_t SCLL;
00396 __O uint32_t CONCLR;
00397 __IO uint32_t MMCTRL;
00398 __IO uint32_t ADR1;
00399 __IO uint32_t ADR2;
00400 __IO uint32_t ADR3;
00401 __I uint32_t DATA_BUFFER;
00402 __IO uint32_t MASK0;
00403 __IO uint32_t MASK1;
00404 __IO uint32_t MASK2;
00405 __IO uint32_t MASK3;
00406 } LPC_I2C_TypeDef;
00408
00409
00410
00414 typedef struct
00415 {
00416 __IO uint32_t MOD;
00417 __IO uint32_t TC;
00418 __O uint32_t FEED;
00419 __I uint32_t TV;
00420 uint32_t RESERVED0;
00421 __IO uint32_t WARNINT;
00422 __IO uint32_t WINDOW;
00423 } LPC_WDT_TypeDef;
00425
00426
00427
00431 typedef struct
00432 {
00433 __IO uint32_t CR;
00434 __IO uint32_t GDR;
00435 uint32_t RESERVED0;
00436 __IO uint32_t INTEN;
00437 __IO uint32_t DR[8];
00438 __I uint32_t STAT;
00439 } LPC_ADC_TypeDef;
00441
00442
00443
00447 typedef struct
00448 {
00449 __IO uint32_t CNTL;
00450 __IO uint32_t STAT;
00451 __IO uint32_t EC;
00452 __IO uint32_t BT;
00453 __IO uint32_t INT;
00454 __IO uint32_t TEST;
00455 __IO uint32_t BRPE;
00456 uint32_t RESERVED0;
00457 __IO uint32_t IF1_CMDREQ;
00458 __IO uint32_t IF1_CMDMSK;
00459 __IO uint32_t IF1_MSK1;
00460 __IO uint32_t IF1_MSK2;
00461 __IO uint32_t IF1_ARB1;
00462 __IO uint32_t IF1_ARB2;
00463 __IO uint32_t IF1_MCTRL;
00464 __IO uint32_t IF1_DA1;
00465 __IO uint32_t IF1_DA2;
00466 __IO uint32_t IF1_DB1;
00467 __IO uint32_t IF1_DB2;
00468 uint32_t RESERVED1[13];
00469 __IO uint32_t IF2_CMDREQ;
00470 __IO uint32_t IF2_CMDMSK;
00471 __IO uint32_t IF2_MSK1;
00472 __IO uint32_t IF2_MSK2;
00473 __IO uint32_t IF2_ARB1;
00474 __IO uint32_t IF2_ARB2;
00475 __IO uint32_t IF2_MCTRL;
00476 __IO uint32_t IF2_DA1;
00477 __IO uint32_t IF2_DA2;
00478 __IO uint32_t IF2_DB1;
00479 __IO uint32_t IF2_DB2;
00480 uint32_t RESERVED2[21];
00481 __I uint32_t TXREQ1;
00482 __I uint32_t TXREQ2;
00483 uint32_t RESERVED3[6];
00484 __I uint32_t ND1;
00485 __I uint32_t ND2;
00486 uint32_t RESERVED4[6];
00487 __I uint32_t IR1;
00488 __I uint32_t IR2;
00489 uint32_t RESERVED5[6];
00490 __I uint32_t MSGV1;
00491 __I uint32_t MSGV2;
00492 uint32_t RESERVED6[6];
00493 __IO uint32_t CLKDIV;
00494 } LPC_CAN_TypeDef;
00496
00497 #if defined ( __CC_ARM )
00498 #pragma no_anon_unions
00499 #endif
00500
00501
00502
00503
00504
00505 #define LPC_FLASH_BASE (0x00000000UL)
00506 #define LPC_RAM_BASE (0x10000000UL)
00507 #define LPC_APB0_BASE (0x40000000UL)
00508 #define LPC_AHB_BASE (0x50000000UL)
00509
00510
00511 #define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000)
00512 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000)
00513 #define LPC_UART_BASE (LPC_APB0_BASE + 0x08000)
00514 #define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000)
00515 #define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000)
00516 #define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000)
00517 #define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000)
00518 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
00519 #define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000)
00520 #define LPC_SSP0_BASE (LPC_APB0_BASE + 0x40000)
00521 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
00522 #define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
00523 #define LPC_CAN_BASE (LPC_APB0_BASE + 0x50000)
00524 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x58000)
00525
00526
00527 #define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000)
00528 #define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000)
00529 #define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000)
00530 #define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000)
00531 #define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000)
00532
00533
00534
00535
00536 #define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
00537 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
00538 #define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE )
00539 #define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE)
00540 #define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE)
00541 #define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE)
00542 #define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE)
00543 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
00544 #define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
00545 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
00546 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
00547 #define LPC_CAN ((LPC_CAN_TypeDef *) LPC_CAN_BASE )
00548 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
00549 #define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
00550 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
00551 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
00552 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
00553 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
00554
00555 #ifdef __cplusplus
00556 }
00557 #endif
00558
00559 #endif